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ASAHI KASEI
[AK2306/LV]
AK2306/2306LV
Dual PCM CODEC for ISDN/VoIP TERMINAL ADAPTER
GENERAL DESCRIPTION
AK2306 is a dual PCM CODEC-Filter most suitable for ISDN Terminal Adapter. It includes Selectable A-law/u-law function, Internal Gain Adjustment from +6dB to -18dB by 1dB step control, Selectable 16Hz/20Hz Ring Tone Generator for SLIC. All of these functions are controlled by the internal register accessed through the serial interface. PCM interface of AK2306 accepts Long Frame, Short Frame clock formats and GCI format. 64 x N kHz(128k-4096kHz) clock input is available for PCM interface. AK2306 and AK2306LV are pin-compatible, but different products which power supply voltage are 5.0V and 3.3V,respectively.
- Dual
FEATURE
PCM CODEC and Filtering systems for ISDN Terminal Adapter - Selectable Ring Tone Generator for SLIC 16Hz or 20Hz tone is available. - Independent functions on each channel controlled by the internal register - Power Down Mode - Mute - Gain Adjustment: +6 to -18dB (1dB step) - Selectable PCM Data Interface Timing: Long Frame / Short Frame/GCI - Variable PCM Data Rate: 64k x N [Hz] (128k - 4.096MHz) - OP Amp for External Gain Adjustment - A-law/u-law Register Selectable - Serial Interface to access the internal register - Power on Reset - Single Power Supply Voltage - +5.0V 5% (AK2306) - +3.3V 0.3V (AK2306LV) - Low Power Consumption
PACKAGE
- 24pinVSOP 7.9 x 7.6 mm (0.5mm pin pitch)
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[AK2306/LV]
CONTENTS
ITEMS - BLOCK DIAGRAM............................................. - PIN ASSIGNMENT............................................. - PIN CONDITION................................................ - PIN FUNCTION................................................. - FUNCTIONAL DESCRIPTION.............................. LONGFRAME/SHORTFRAME/GCI - MUTE.................................................... 12 - GAIN ADJUSTMENT................................. 13 - RING TONE GENERATOR .......................... - RESET ....................................................... 14 15 PAGE 3 4 5 6 9
- CIRCUIT DESCRIPTION...................................... 8 - PCM INTERFACE...................................... 9
- POWER DOWN........................................ 16 - SERIAL INTERFACE................................ 18 - REGISTER....................................................... 22 - ABSOLUTE MAXIMUM RATINGS......................... 25 - RECOMMENDED OPERATING CONDITIONS........ 25 - ELECTRICAL CHARACTERISTICS....................... 25 - APPLICATION CIRCUIT EXAMPLE....................... 34 - PACKAGE INFORMATION.................................. 36
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[AK2306/LV]
BLOCK DIAGRAM
GST0 VFTP0 VFTN0 VR0 VFR0 GSR0 GST1 VFTP1 VFTN1 VR1 VFR1 GSR1 TNOUT VREF LPC
GA0T AMPT0 GA0R
AAF0
CODEC CH0
PCM I/F FS0
SMF0
DX DR FS
AMPR0
BCLK
GA1T AMPT1 GA1R AMPR1
AAF1
CODEC CH1 FS1
SMF1
RING TONE GENERATOR BGREF
PLL
RXVlm0
TXVlm1 TXVlm0 RXVlm1
PWDN
A/u_SEL
Mut0
Mut1
VDD VSS Power on Reset
Internal Register
Serial I/F
R
it
SCLK DATA CSN
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[AK2306/LV]
PIN ASSIGNMENT
VFTP1 VFTN1 GST1 GSR1 VFR1 VR1 VDD FS BCLK DX DR TNOUT
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VREF VFTP0 VFTN0 GST0 GSR0 VFR0 VSS VR0 LPC CSN DATA SCLK
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[AK2306/LV]
PIN CONDITION
Pin# Name I/O Pin type AC load (MAX.) DC load (MIN.)
Outout status (Power down mode) Output status (Reset)
Remarks
VFTP1 Analog VFTN1 Analog GST1 50pF Analog Hi-Z Hi-Z 10k(*1) GSR1 50pF O Analog Hi-Z Hi-Z 10k (*1) VFR1 I Analog VR1 50pF O Analog Hi-Z Hi-Z 10k VDD FS I TTL/CMOS(*3) BCLK I TTL/CMOS(*3) DX 15pF O CMOS Hi-Z Hi-Z DR I TTL/CMOS(*3) TNOUT 15pF O CMOS L L SCLK I TTL/CMOS(*3) DATA 15pF I/O TTL/CMOS(*3) Input Input CSN I TTL/CMOS(*3) LPC O Analog 0.22uF (*2) VSS VR0 50pF O Analog Hi-Z Hi-Z 10k VFR0 I Analog GSR0 50pF O Analog Hi-Z Hi-Z 10k (*1) GST0 50pF I Analog Hi-Z Hi-Z 10k (*1) VFTN0 O Analog VFTP0 O Analog VREF O Analog 1.0 uF (*2) *1) DC load(MIN.) includes a feedback resistance of input/output op-amp. *2)External capacitance should be connected to VSS. *3)TTL level is applied only for the input level of AK2306LV. Output level for both AK2306 and AK230LV,and the input level of AK2306 are CMOS level.
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[AK2306/LV]
PIN FUNCTION
Pin# Name 1 VFTP1 I/O I Function Positive analog input of the transmit OPamp(AMPT1) for channel 1. Transmit gain is defined by the ratio of R2/R1. R1 is the external input resister connected to this pin. R2 is the external feedback resister connected between this pin and GST1. Negative analog input of the transmit OPamp(AMPT1) for channel 1. Output of the transmit OPamp(AMPT1) for channel 1. The external feedback resister is connected between this pin and VFTP1. Output of the receive OPamp(AMPR1) for channel 1. Negative analog input of the receive OPamp(AMTR1) for channel 1. Receive gain is defined by the ratio of R4/R3. R3 is the external input resister connected to this pin. R4 is the external feedback resister connected between this pin and VR1. Analog Output equivalent to the received PCM data for channel 1. Output gain is adjusted by the GA1R. Negative analog input of the transmit OPamp(AMPT0) for channel 0. Transmit gain is defined by the ratio of R2/R1. R1 is the external input resister connected to this pin. R2 is the external feedback resister connected between this pin and GST0. Positive analog input of the transmit OPamp(AMPT0) for channel 0. Output of the transmit OPamp(AMPT0) for channel 0. The external feedback resister is connected between this pin and VFTP0. Analog Output equivalent to the received PCM data for channel 0. Output gain is adjusted by the GA0R Negative analog input of the receive OPamp(AMTR0) for channel 0. Receive gain is defined by the ratio of R4/R3. R3 is the external input resister connected to this pin. R4 is the external feedback resister connected between this pin and VR0. Output of the receive OPamp(AMPR0) for channel 0. Serial output of PCM data. The channel 1 data is output following the channel 0 data. The PCM data rate is synchronized with BCLK. This output remains in the high impedance state except for the period of transmitting PCM data. Serial input of PCM data. The channel 1 data is received following the channel 0 data. The PCM data rate is synchronized with BCLK. Frame sync input. This clock is input for the internal PLL which gerenates the internal system clocks. FS must be 8kHz clock which is synchronized with BCLK. Bit clock of PCM data interface. This clock defines the input/output timing of DX and DR. The frequency of BCLK should be 64 x N kHz(128k - 4096kHz).
2 3 4 5
VFTN1 GST1 GSR1 VFR1
I O O I
6 22
VR1 VFTN0
O I
23 21 17 19
VFTP0 GST0 VR0 VFR0
I O O I
20 10
GSR0 DX
O O
11
DR
I
8
FS
I
9
BCLK
I
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Pin# Name 12 TNOUT 14 13 15 16 24 7 18 DATA SCLK CSN LPC VREF VDD VSS I/O O I/O I I O O Function Ring Tone output pin. 16Hz or 20Hz tone is selected by the internal register. Data input of serial interface. Clock input of serial interface. Read and write enable of serial interface.
[AK2306/LV]
Pin for PLL loop filter. External capacitance(Min 0.22uF) should be connected between this pin and VSS. Analog ground output. External capacitance(1.0 uF) should be connected between this pin and VSS. Positive supply voltage. +5V(AK2306) or +3.3V(AL2306LV) supply. Ground.
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[AK2306/LV]
CIRCUIT DESCRIPTION
Block AMPT0,1 Function Op-amp for input gain adjustment. This op-amp has differential inputs. Adjusting the gain with external resistors. The resistor larger than 10k is recommended for the feedback resistor. AMPT0(1) becomes automatically power down, when CODEC ch0(1) is power down. Op-amp for output gain adjustment. This op-amp is used as an inverting amplifier. Adjusting the gain with external resistors. The resistor larger than 10k is recommended for the feedback resistor. Integrated anti-aliasing filter which prevents signals around the sampling rate from folding back into the voice band. AAF is a 2nd order RC low-pass filter. Converts analog signal to 8bit PCM data according to the companding schemes of ITU recommendation G.711; A-law or u-law. The band limiting filter is also integrated. The selection of companding schemes is set by ALAWN register as follows: "H": u-Law "L": A-Law Expands 8bit PCM data according to A-law or u-law. The selection of companding schemes is set by ALAWN register as follows: "H": u-Law "L": A-Law Extracts the inband signal from D/A output. It also corrects the sinx/x effect of D/A output. Provides the stable analog ground voltage using an on-chip band-gap reference circuit which is temperature compensated. The output voltage is 2.4V for +5V operation(AK2306) or 1.5V for +3.3V operation(AK2306LV). Generates two kinds of tone; 16Hz or 20Hz. Tone selection and Tone ON/OFF is controlled by the registers. Gain selects of analog I/O signals. It is posibble to select gain from +6dB to -18dB (1dB/step). Gain is defined by the internal register. Interface to the internal register by using SCLK, DATA, and CSN pins. PLL generates system clock of AK2306. Reference clock is FS (8KHz). More than 0.22uF of an external capacitance should be connected between LPC and VSS. PCM data rate is available for 64xN(N = 2 to 64)kHz which synchronizes with BCLK. Two kinds of data format (Long Frame, Short Frame) are available. Each data format is automatically detected. PCM data stream, which includes ch0 and ch1 data, is output through DX pin and input through DR pin. Ch1 PCM data stream always follows ch0 PCM data stream.
AMPR0,1
AAF A/D
D/A
SMF BGREF
RING TONE GENERATOR GA0T/R GA1T/R GATN SERIAL I/F PLL PCM I/F
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[AK2306/LV]
FUNCTIONAL DESCRIPTION PCM Data Interface
AK2306 supports the following 3 PCM data formats - Long Frame Sync(LF) - Short Frame Sync(SF) - GCI PCM data of both channels are multiplexed and interfaced through the common pins(DR,DX).The first 8bit is defined as B1 channel and the seconds 8bit is defined as B2 channel in the PCM data stream. The order of PCM data is MSB first in each channel. Selection of the interface mode The GCI and ordinary PCM interface(LF,SF) are selectable through the CPU register as following table. LF and SF is automatically selected by AK2306 by means of detecting the length of 8KHz frame signal.
Register for PCM Interface mode select (Address:101 Bit:0) PCMIF PCM Interface 0 1 LF or SF GCI
Comments
LF/SF are selected automatically
Default on power-on reset =LF/SF mode(PCMIF=0).
LONG FRAME( LF ) / SHORT FRAME ( SF ) Automatic LF/SF selection AK2306 monitors the duration of the "H" level of FS and automatically selects LF or SF interface format.
period of FS="H" more than 2 clocks of BCK 1 clock of BCK
Timing of the interface
Interface format LF SF
8 bits PCM data is accommodated in 1 frame( 125us ) defined by 8kHz frame sync signal. Although there are 64 time slots at maximum in 8kHz frame(when BCK=4.096MHz), PCM data for AK2306 occupy first and second time slot for channel 0 and channel 1,respectively as is indicated in figures of next page. - Frame Sync signal (FS) 8kHz reference signal. This signal indicated the timing and the frame position of 8kHz PCM interface. All the internal clock of the LSI is generated based on this FS signal. - Bit Clock (BCLK) BCLK defines the PCM data rate. BCLK can be varied from 128kHz to 4.096MHz by 64kHz step. - Position of the Ch0,Ch1 PCM data in the DX/DR data flow
B1 and B2 channel of the PCM data channel are assigned to Analog Ch0 and Ch1 as is defined by SEL2B register.
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CH0,1selection (Address:100 Bit:5) SEL2B CH0 0 1 B1 B2 CH1 B2 B1 Remarks Default on Reset
[AK2306/LV]
<2ch Multiplexed> LongFrame
FS BCLK
B1 ch B2 ch
DX DR
Don't care
1 1
2 2
=> =>
3 3
4 4
5 5
6 6
7 7
8 8
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
Don't care
SEL2B=0 SEL2B=1
B1-CHANNEL (CH0) B1-CHANNEL (CH1)
B2-CHANNEL (CH1) B2-CHANNEL (CH0)
ShortFrame
FS BCLK
B1 ch B2 ch
DX DR
Don't care SEL2B=0 SEL2B=1
1 1
=> =>
2 2
3 3
4 4
5 5
6 6
7 7
8 8
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
Don't care
B1-CHANNEL (CH0) B1-CHANNEL (CH1)
B2-CHANNEL (CH1) B2-CHANNEL (CH0)
Not supported
! Important Notice
Please don't stop feeding FS and BCLK except Full power down mode. Internal PLL does free running when either FS or BCLK is not provided. In this case, the frequency of Ring Tone output is not guaranteed.
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GCI ( General Circuit Interface )
GCI format is used for ISDN application. The data format and clocking is showed as Fig X. timing of the interface
[AK2306/LV]
8 bits PCM data is accommodated in 1 frame( 125us ) defined by 8kHz frame sync signal. Although there are 32 time slots at maximum in 8kHz frame(when BCK=4.096MHz), PCM data on GCI occupy first and second time slot for channel 0 and channel 1,respectively.
Frame Sync signal (FS) 8kHz reference signal. This signal indicated the timing and the frame position of 8kHz GCI. All the internal clock of the LSI is generated based on this FS signal. High level duration of the FS is 1 clock period of BCLK. Bit Clock (BCLK) BCLK defines the GCI data rate. The bit rate of GCI data is half of BCLK. BCLK can be varied from 512kHz to 4.096MHz by 128kHz step. Position of the Ch0,Ch1 GCI data in the DX/DR data flow
B1 and B2 channel of the GCI data channel are assigned to Analog Ch0 and Ch1 as is defined by SEL2B register as same way as PCM interface. CH0,1selection( Address:100 Bit:5) SEL2B CH0 0 1 B1 B2
CH1 B2 B1
Remarks Default on Reset
<2ch Multiplex>
FS BCLK
B1 ch B2 ch
DX DR
Don't care
1 1
2 2
=> =>
3 3
4 4
5 5
6 6
7 7
8 8
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
Don't care
SEL2B=0 SEL2B=1
B1-CHANNEL (CH0) B1-CHANNEL (CH1)
B2-CHANNEL (CH1) B2-CHANNEL (CH0)
Not supported
! Important Notice
Please don't stop feeding FS and BCLK except Full power down mode. Internal PLL does free running when either FS or BCLK is not provided. In this case, the frequency of Ring Tone output is not guaranteed.
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[AK2306/LV]
MUTE
The output on each channel can be muted independently through the CPU register as shown in the table. Mute register( Address:100 Bit:5,4 )
MTCH0,1 0 1
Operation Normal Mute
DX pin PCM data output High-Impedance(* 1)
VRX pin CODEC analog output AGND*
(*1) MTCH0 and MTCH1 are the mute control bit for CH0 and CH1,respectively. B1 and B2 channel muted by MTCH0/1 is defined by SEL2B bit shown in the PCM Interface section. LF Mode CH0 mute (MTCH=1, MTCH1=0, SEL2B=0)
FS0 BCLK DX DR
Don't care B1-CHANNEL(CH0)
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
Don't care
B2-CHANNEL(CH1)
VRX0 VRX1
GCI mode
: :
CODEC CH0 analog output is always at AGND level. CODEC CH1 analog output is the signal converted from the PCM data of CH1 input through DR pin.
CH0 mute (MTCH0=1, MTCH1=0, SEL2B=0)
FS0 BCLK DX DR
Don't care B1-CHANNEL(CH0)
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
Don't care
B2-CHANNEL(CH1)
VRX0 VRX1
: :
CODEC CH0 analog output is always at AGND level. CODEC CH1 analog output is the signal converted from the PCM data of CH1 input through DR pin.
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[AK2306/LV]
GAIN ADJUSTMENT
Analog input/output gain can be adjusted at the range from +6dB to -18dB by 1.0dB step through CPU register. VR Register( Address:011 -000 Bit:4 -0)
GanT4 GanR4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
GanT3 GanR3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1
GAnT2 GAnR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ---
GAnT1 GAnR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ---
GAnT0 GAnR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ---
Gain [dB] +6 +5 +4 +3 +2 +1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18
Remarks
Default
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[AK2306/LV]
RING TONE GENERATOR
Ring tone generator generates two kinds of ring tone, 16Hz and 20Hz. The frequency of the tone can be selected by CPU register. Tone frequency selection Tone Selection register (Address: 101, Bit: 4)
TNFQ 0 1
Tone output enable
Tone Frequency 16Hz 20Hz
Remarks Default
Tone output can be enabled/disabled through CPU register.
RING TONEGEN Enable (Address: 100, Bit: 2) PDTN 1 0 RING TONE GENERATOR Power Down* Tone output enabled Remarks Default
* When Power down is selected, TNOUT pin output is fixed to "L" level.
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[AK2306/LV]
RESET
Power on Reset AK2306 automatically generates the internal reset pulse which resets all the circuit that is necessary to start the initialization after the power on reset. The CPU registers are set to the default value. After the internal reset pulse is generated, CODEC Ch0/Ch1 starts the initialization procedure by being fed FS signal, and it takes 180ms( typ.), 350ms(max) to complete the initialization after the detection of power on. Power up slope to enable the Power-on Reset
When power-up slope is no longer than 50ms(=5tau:tau is time constant), Power On Reset works normally. When the time is longer than 50ms, Power On Reset is not activated and no internal registers are initialized. In this case all registers must be written through CPU interface.
NOTE) For stable operation after power up, we recommend to write all register value through CPU interface after power up. Recommended start up procedure
The following start up procedure is recommended when AK2306/LV is going to power up.
Power up
Wait 200ms *In case of VDD rising time =50ms(=5tau)
- FS="L" - BCLK="L" When 1stFS and BCLK are set to "L", CODEC ch0,ch1 dose not interface with external devices.
Write data to the internal register through serial I/F
- Write data to the internal register before CODEC starts working.
Supply FS and BCLK
- CODEC Initialization starts. Wait 130ms - CODEC Initialization complete. CODEC starts working
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[AK2306/LV]
POWER
DOWN
Power consumption is reduced in the power down mode. In the power down mode, the current fed to analog circuits and the clock for digital circuits, are stopped, and the relating circuits hold its status. There are two power down modes. - Power down for all circuits - Power down by block * In the power down mode, the output pins of corresponding blocks turn to Hi-Z except TNOUT pin.(See page 5) POWER DOWN MODE SETTING 2 power down modes Mode Circuits Registers Operation for "0"/"1" Note - CPU Registers are not reset. - Serial I/F is available. - No need to supply FS, BCLK.
All circuit
All
PD
"0" : Normal "1" : Power down
CODEC CH0 CODEC CH1 RING TONEGEN
PDCH0
Block
PDCH1
"0" : Normal "1" : Power down
PDTN
- Keep supplying FS, even when CODEC CH0,1 are in power down mode (see page10,11). - When CODEC CHn(n=0,1) is in power down mode, the functions below are active: (1) AMPTn(n=0,1) Input/Output (2) TNOUT Output Please refer next page table in deltail.
CANCELLATION OF POWER DOWN : CODEC When power down mode for CODEC CH0/CH1 is cleared, the CODEC circuitry starts to be initialized. It takes 130mS(typ.). When full circuit power down mode for CODEC is cleared, AK2306/LV starts the same wake up sequence as one at power on. It takes 250ms(Typ) Wake up time for Tone generator is 125us(Typ).
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POWER DOWN BLOCK REGISTER AMPT0 GA0T Channel 0 AAF0 CODEC CH0 SMF0 GA0R AMPR0 AMPT1 GA1T Channel 1 AAF1 CODEC CH1 SMF1 GA1R AMPR1 PCM I/F RING TONEGEN PLL BGREF SERIAL I/F ALL BLOCK PD OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF CODEC CH0 PDCH0 CODEC CH1 PDCH1 CODEC CH0&1 PDCH0 PDCH1 RING TONEGEN PDTN
[AK2306/LV]
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[AK2306/LV]
SERIAL INTERFACE
The internal registers can be read/written with SCLK, DATA, and CSN pins. 1word consists of 16bits. The first 4bits are the instruction code which specifies read/write. The following 3bits specify the address. The rest of 8bits are for setting registers. B15 I3 B14 I2 B13 I1 B12 I0 B11 A2 B10 A1 Address (3bit) B9 A0 B8 * * B7 D7 B6 D6 B5 D5 B4 D4 B3 D3 B2 D2 B1 D1 B0 D0
Instruction code (4bit)
Data for internal registers (8bit)
*)Dummy bit for adjusting the I/O timing when reading register.
INSTRUCTION CODEC
I3 1 1
I2 1 1
I1 1 1
I0 0 1
Read/Write Read Write No action
Other codes
SCLK and WRITE/READ
(1) Input data are loaded into the internal shift register at the rising edge of SCLK. (2) The rising edge of SCLK is counted after the falling edge of CSN. (3) When CSN is "L" and more than 16 SCLK pulses: th [WRITE] Data are loaded into the internal register at the rising edge of the SCLK 16 pulse. th [READ] DATA pin is switched to an input pin at the falling edge of the SCLK 16 pulse.
CSN and WRITE / READ CANCELLATION
(1) WRITE is cancelled when CSN goes up before the rising edge of the SCLK 16 pulse. th (2) READ is cancelled when CSN goes up before the falling edge of the SCLK 16 pulse.
SERIAL WRITE / READ (SERIAL ACCESS)
th
(1) CSN must go up to "H" before the next access in successive access. (2) When the next access is going to be done , if CSN remains to be "L", successive access can not be done.
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WRITE Continuous SCLK
Must goes up once
[AK2306/LV]
CSN SCLK DATA
Z 1 2 3 4 5 6 7 8 9 16
Goes up anytime after SCLK 16th pulse
1
2
3
4
8
9
15
16
1
1
1
1
0
0 Address "000"
0
*
D7
D0
Z
1
1
1
1
D7
D1
D0
Z
Instruction Code
Write data to address"000"
WRITE at the rising edge of SCLK 16th pulse
Instruction Code
Write data
Burst SCLK SCLK can be stop at "H" level or "L" level at anytime during the write cycle. After resuming the SCLK, write cycle is retrieved normally.
Must go up once Goes up anytime after SCLK 16th pulse
CSN SCLK DATA
Z 1 2 3 4 5 6 7 8 9 16
1
1
1
1
0
0 Address "000"
0
*
D7
D0
Z
Instruction Code
Write data to address "000"
WRITE at the rising edge of SCLK 16th pulse
CANCELLATION
CSN goes "H" before the rising edge of 16th SCLK pulse
CSN SCLK DATA
Z 1 2 3 4 5 6 7 8 9 16
1
1
1
1
0
0 Address "000"
0
*
D7
D0
Z
Instruction Code
Write data to address"000"
Write is not Excuted
Z
DATA pin: Input mode (Hi-Z)
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SERIAL ACCESS Serial access with CSN staying "L" during the serise of write cycle.
CSN SCLK DATA
Z 1 2 3 4 5 6 7 8 9 16 1 2 3 4 8 9
[AK2306/LV]
15
16
1
1
1
1
0
0
0
*
D7
D0
Z
1
1
1
1
D7
D1 Write data
D0
Z
Instruction Code
Address "000"
Write data to Address"000" EXCUTE!
Instruction Code
NOT EXCUTED!
READ CONTINOUS SCLK
Must go up once Can be going up at anytime after SCLK 16th pulse
CSN SCLK DATA
Z 1 2 3 4 5 6 7 8 9 16
1
2
3
4
8
9
15
16
1
1
1
0
A2
A1
A0
Z
D7
D0
Z
1
1
1
0
D7
D1 D0
Z
Read Instruction
Address
Read Data
Read Instruction
Read Data
Data output starts at the falling edge of SCLK 8th pulse
Read period until the earlier edge of either CSN rising or SCLK 16th pulse falling
Burst SCLK
Must go up once Can be going up at anytime after SCLK 16th pulse
CSN SCLK DATA
Z 1 2 3 4 5 6 7 8 9 16
1
1
1
0
A2
A1
A0
Z
D7 Read Data
D0
Z
Read Instruction
Address
Read output starts at the falling edge of SCLK 8th pulse
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SERIAL ACCESS Serial access with CSN staying "L" during the serise of read cycle.
[AK2306/LV]
CSN
SCLK DATA
Z
1
2
3
4
5
6
7
8
9
16
1
2
3
4
8
9
15
16
1
1
1
0
0
0 Address "000"
0
Z
D7
D0
Z
1
1
1
0
Z
Read Instruction
Read data READ EXCUTED!
Read Instruction READ NOT EXCUTED!
DISCORD OF INSTRUCTION CODE
CSN SCLK DATA
Z 1 2 3 4 5 6 7 8 9 16
I3
I2
I1
I0
A2
A1 A0 Address
Z
IInstructions except specified 0bbb 10bb 110b (b=0 or 1)
WRITE/READ NOT EXCUTED!
Z
DATA pin: Input mode (Hi-Z)
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[AK2306/LV]
REGISTER
Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5
MAP
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
A2 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1
* * * * * * * * *
D7 0 0 0 0 0 0
D6 0 0 0 0 0 0
D5 MTCH1 0
D4 GA0R4 GA1R4 GA0T4 GA1T4 MTCH0 0
D3 GA0R3 GA1R3 GA0T3 GA1T3 PD TNFQ
D2 GA0R2 GA1R2 GA0T2 GA1T2 PDTN ALAWN
D1 GA0R1 GA1R1 GA0T1 GA1T1 PDCH1 SEL2B
D0 GA0R0 GA1R0 GA0T0 GA1T0 PDCH0 PCMIF
Reserved Reserved
*)Dummy Bit Note) All registers except address(000 - 011), Bit5(D5) can be read/write. Note) Please write "all 0's" for address(000 - 100), Bit7,6(D7,D6) and address(101), Bit7,6,5,4(D7 - D4) for normal operation. Note) Address(000 - 011),Bit5(D5) can not be write and "0" data will be output when it is accessed to read. INITIALIZATION OF REGISTERS The registers are initialized at POWER ON RESET only. Power on reset may not be excuted due to the difference of power up time constant. Thus it is highly recommended that all the register (address(000 - 101) ) are to be written at the time of the power up and after the abnormal circumstances happens such as micro interrupt of the power line or mal operation due to lightning. REGISTER FUNCTION
Address 000
001
Bit 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
Name GA0R0 GA0R1 GA0R2 GA0R3 GA0R4 0 0 GA1R0 GA1R1 GA1R2 GA1R3 GA1R4 0 0
Default 0 1 1 0 0 0 0 0 1 1 0 0 0 0
Function Receive gain adjustment on ch0 +6 to -18dB by 1.0dB step 00000: +6dB 11xxx: -18dB
Refer
Test mode Please write all "0". Receive gain adjustment on ch1 +6 to -18dB by 1.0dB step 00000: +6dB 11xxx: -18dB
Test mode Please write all "0".
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Address 010 Bit 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 101 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Name GA0T0 GA0T1 GA0T2 GA0T3 GA0T4 0 0 GA1T0 GA1T1 GA1T2 GA1T3 GA1T4 0 0 PDCH0 PDCH1 PDTN PD MTDX0 MTDX1 0 0 PCMIF SEL2B ALAWN TNFQ 0 0 0 0 Default 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Function Transmit gain adjustment on ch0 +6 to -18dB by 1.0dB step 00000: +6dB 11xxx: -18dB Refer
[AK2306/LV]
011
Test mode Please write all "0". Transmit gain adjustment on ch1 +6 to -18dB by 1.0dB step 00000: +6dB 11xxx: -18dB
100
Test mode Please write all "0". CODEC CH0,1 Power down control 0: Power ON 1: Power OFF RING TONEGEN Power down control 0: Power ON 1: Power OFF Full Power down 0: Power ON 1: Power OFF Mute control: VR0.VR1,DX pin 0: Normal output 1: Mute Test mode Please write all "0". PCM Interface select 0: LF/SF 1: GCI PCM data channel select 0: CH0 -> B1 1: CH1 -> B1 A/u-law select 0: A-law 1: u-law Tone frequency select 0: 16Hz 1: 20Hz Test mode Please write all "0".
110
Reserved
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Address 111 Bit 0 1 2 3 4 5 6 7 Name Default 0 0 0 0 0 0 0 0 Function Reserved Refer
[AK2306/LV]
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[AK2306/LV]
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Min Max Power Supply Voltages Analog/Digital Power Supply VDD -0.3 6.5 VSS Voltage VSS -0.1 0.1 Digital Input Voltage VTD -0.3 VDD+0.3 Analog Input Voltage VTA -0.3 VDD+0.3 Input current (except power supply pins) IIN -10 10 Storage Temperature Tstg -55 125 Warning: Exceeding absolute maximum ratings may cause permanent damage. Normal operation is not guaranteed at these extremes. Units V V V V mA o C
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min 4.75 3.0 -40 Typ 5.0 3.3 8 Max 5.25 3.6 85 Units V V C kHz
o
Power Supplies Analog/Digital power supply( AK2306 ) VDD Power Supplies Analog/Digital power supply( AK2306 LV) VDD Ambient Operating Temperature Ta Frame Sync Frequency FS0,FS1 Note) All voltages reference to ground : VSS=0V
ELECTRICAL CHARACTERISTICS
Unless otherwise noted, guaranteed for VDD=+5V +/- 5%(AK2306), VDD=+3V+/-0.3V(AK2306LV), o Ta = -40 ~ +85 C, FS=8kHz.
DC Characteristics
Parameter Power Consumption BCLK=2048kHz Output High Voltage (CMOS level) Output Low Voltage (CMOS level) Input High Voltage1 (CMOS level) Input High Voltage2 (TTL level) Input Low Voltage1 (CMOS level) Input Low Voltage2 (TTL level) Input Leakage Current Input Capacitance Output Leakage Current Power Consump.@PD Symbol Conditions PDD1 PDCH0,1 PDDT0,1=0,0 All output unloaded PDD2 PDCH0,1 PDDT0,1=1,0 All output unloaded VOH IOH=-1.6mA VOL VIH1 VIH2 VIL1 VIL2 Ii Ci Io Tri-state mode PDDd -10 -10 IOL=1.6mA 0.7VDD 2.4 0.3VDD 0.8 +10 5 +10 Min Typ 65 mW 35 0.8VDD 0.4 V V V V V V uA pF uA mW Max Units
2.5
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ASAHI KASEI CODEC
Absolute Gain ( AK2306: VDD=5.0V +/-5%, AK2306LV VDD=3.3V +/-0.3V ) Parameter Conditions Min Analog Input Level Input: AK2306 0dBm0@1020Hz AK2306LV Absolute Transmit Gain -0.6 Analog Output Level Input: AK2306 0dBm0@1020Hz AK2306LV Absolute Receive Gain -0.6 Maximum Overload Level +3.14dBm0 AK2306 AK2306LV Gain Tracking Parameter Transmit Gain Tracking Error
[AK2306/LV]
Typ 0.849 0.531 0.849 0.531 1.219 0.762
Max
Units Vrms dB Vrms dB Vrms
0.6
0.6
Receive Gain Tracking Error
Conditions Reference Level: -55dBm0 ~-50dBm0 -10dBm0 -50dBm0 ~-40dBm0 1020Hz Tone -40dBm0 ~ 3dBm0 Reference Level: -55dBm0 ~-50dBm0 -10dBm0 -50dBm0 ~-40dBm0 1020Hz Tone -40dBm0 ~ 3dBm0
Min -1.2 -0.4 -0.2 -1.2 -0.4 -0.2
Typ -
Max 1.2 0.4 0.2 1.2 0.4 0.2
Units dB
dB
Frequency Response Parameter Transmit Frequency Response
Receive Frequency Response
Conditions Relative to: 0.05kHz 0dBm0@1020Hz 0.06kHz 0.2kHz 0.3 ~3.0kHz 3.4kHz 4.0kHz Relative to: 0 ~3.0kHz 0dBm0@1020Hz 3.4kHz 4.0kHz
Min -1.8 -0.15 -0.8 -0.15 -0.8 -
Typ -
Max -30 -26 0 0.15 0 -14 0.15 0 -14
Units
dB
dB
Distortion Parameter Transmit Signal to Distortion
Receive Signal to Distortion
Conditions -40dBm0 ~-45dBm0 -30dBm0 ~-40dBm0 0dBm0 ~-30dBm0 1020Hz Tone -40dBm0 ~-45dBm0 -30dBm0 ~-40dBm0 0dBm0 ~-30dBm0 1020Hz Tone
Single Frequency Distortion Transmit Single Frequency Distortion Receive Intermodulation Distortion -6dBm@860Hz,1380Hz Note) C-message Weighted for u-Law, Psophometric Weighted for A-Law
Min 25 30 36 25 30 36 -
Typ -
Max -46 -46 -42
Units dB
dB dB dB dB
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Envelope delay Distortion Parameter Transmit Delay, Absolute Transmit Delay, Relative Conditions f =1600Hz f =500Hz ~600Hz f =600Hz ~1000Hz f =1000Hz ~2600Hz f =2600Hz ~2800Hz f =2800Hz ~3000Hz f =1600Hz f =500Hz ~1000Hz f =1000Hz ~1600Hz f =1600Hz ~2600Hz f =2600Hz ~2800Hz f =2800Hz ~3000Hz Min -40 -30 Typ -
[AK2306/LV]
Max 560 220 145 75 105 155 450 90 125 175 Units us
us
Relative to f=1600Hz Receive Delay, Absolute Receive Delay, Relative
us
us
Relative to f=1600Hz
Noise Parameter 1) Idle Channel Noise AD 2) Idle Channel Noise DA Noise, Single Frequency Conditions u-law, C-message A-law, Psophometric u-law, C-message A-law, Psophometric VFXIN = 0 Vrms, DR = DX f=0 ~100kHz PSRR, Transmit AVDD=DVDD=5V100mVop f=0 ~50kHz PSRR, Receive AVDD=DVDD=5V100mVop f=0 ~50kHz Spurious Out-of-Band Signal 0dBm0, 4.6 ~7.6kHz 3) at VRX Output 0.3 ~3.4kHz 7.6 ~8.4kHz PCM CODE 8.4 ~100kHz Note 1) Analog Input = Analog Ground Note 2) Digital Input(DR) = +0 Code Note 3) Not tested in production Test. Parameters guaranteed by design. Interchannel Crosstalk Parameter Transmit to Receive Receive to Transmit Transmit to Transmit Receive to Receive Parameter Load Resistance Load Capacitance VDD=5V Output voltage Swing VDD=3.3V Min 40 40 Typ 5 -85 5 -85 Max 10 -80 10 -80 -53 -30 -40 -32 Units dBrnC0 dBm0p dBrnC0 dBm0p dBm0 dB dB
dB
Conditions 0dBm0@VFXIN, Idle PCM code 0dBm0 code level, VFXIN = 0 Vrms 0dBm0@VFXIN, Idle PCM code 0dBm0 code level, VFXIN = 0 Vrms Conditions
Min Min 10 -
Typ Typ 3.6 2.25
Max -75 -75 -75 -75 Max 50 -
Units dB dB dB dB Units kohm pF Vp-p
Analog Interface Transmit Amplifier
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Analog Interface Receive Output Parameter Output voltage(AGND level) Load Resistance Load Capacitance Output voltage Swing
[AK2306/LV]
(AK2306 : VDD 5.0V5%, AK2306LV : VDD 3.3V0.3V) Conditions Min Typ Max AK2306 2.3 2.4 2.5 +0 PCM code input AK2306LV 1.5 10 50 AK2306 3.6 AK2306LV 2.25 -
Units V kohm pF Vp-p
Analog Interface Receive Output Amplifier
Parameter Input Resistance Load Resistance Load Capacitance Output Voltage Swing
Conditions
AK2306 AK2306LV
Min 10 10 -
Typ 3.6 2.25
Max 50 -
Units M ohm k ohm pF Vp-p
VOLUME ( GA0T,GA0R,GA1T,GA1R)
Parameter Step margin Pin Conditions Relative to: 0dB Min -1.0 typ max Unit +1.0*) dB
*)Monotonus increase/decrease is guranteed RING TONE GENERATOR
Parameter Signal frequency 16Hz/20Hz Tone Duty Conditions No Jitter on FS 8KHz frame signal No Jitter on FS 8KHz frame signal Min -5% 49 typ 16/20 50 max +5% 51 Unit Hz %
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ASAHI KASEI PCM INTERFACE ( Long Frame, Short Frame, GCI )
o
[AK2306/LV]
Unless otherwise noted, the specification applies for TA = -40 to +85 C, VDD = 5V5%/3V0.3V,VSS = 0V and FS0= 8kHz. All timing parameters are measured at VOH = 0.8VDD and VOL =0.4V. Parameter FS Frequency BCLK Frequency BCLK Pulse Width High BCLK Pulse Width Low Rising Time: (BCLK,FS0,FS1,DX0,DX1,DR0,DR1) Falling Time: (BCLK,FS0,FS1,DX0,DX1,DR0,DR1) Hold Time: BCLK Low to FS High Setup Time: FS High to BCLK Low Setup Time: DR to BCLK Low Hold Time: BCLK Low to DR Delay Time: BCLK High to DX valid Long Frame Hold Time: 2 period of BCLK Low to FS Low Delay Time: FS or BCLK High, whichever is later,to DX valid Note1) Delay Time: BCLK Low to DX High-Z Note1) FS Pulse Width Low Short Frame Hold Time: BCLK Low to FS Low Setup Time: FS Low to BCLK Low Delay Time: BCLK Low to DX High-Z Note1) GCI BCLK Frequency Delay Time: Second BCLK Low to DX High-Z Setup Time: DR to Second BCLK High Hold Time: Second BCLK High to DR 1/tPBG tDZCG tSDBG tHBDG 512 10 40 40 4096 60 kHz ns Fig3 ns ns tHBFS tSFBS tDZCS 40 40 10 60 ns ns ns Fig2
nd
Symbol 1/tPF 1/tPB tWBH tWBL tR tF tHBF tSFB tSDB tHBD Note1) tDBD
Min 128 80 80
Typ 8
Max 4096
Units Ref Fig kHz kHz ns ns
40 40 40 70 40 40 60
ns ns ns ns ns ns ns
Fig1 Fig2 Fig3
tHBFL tDZFL tDZCL tWFSL
40 60 10 1 60
ns ns Fig1 ns BCL K
Note1) Measured with 150pF Load capacitance and driving two LSTTLs
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ASAHI KASEI
tF BCLK tSF tHBFL tRB tWB tWB tPB
[AK2306/LV]
FS tHB DX MSB 2 3 tSD DR MS 2 3 4 tHB 4 5 6 7 8 5 6 7 8 tDZF tDB tDZ
FS tPF tWFSL
Fig1 PCM Interface Timing
tRB
< Long Frame >
tFB BCLK
tWB
tWBH
tPB
tSF
tHBF
FS tHBF DX MS 2 3 tSD DR MS 2 3 4 4 tHB 5 6 7 8 5 6 7 8 tSFB tDBD tDBD tDZC
Fig2
PCM Interface Timing
< Short Frame >
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FS 1 2 3 4 5 6 7 8 9 10111213141516 BCLK tDB DX MS 2 3 tSDB DR MS 2 3 4 4 5 tHBD 5 6 7 8 MS 2 3 4 5 6 7 6 7 8 tDZC MS 2 3 4 tWB 5 6 7 tPB tWB
[AK2306/LV]
8
8
BCLK tSF tHBF tWFS FS tHB DX 1 2 3 tDZF
Fig3
PCM Interface Timing
< GCI >
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ASAHI KASEI SERIAL INTERFACE
Parameter SCLK Frequency SCLK Pulse Width High SCLK Pulse Width Low CSN Pulse Width Low Hold Time: SCLK High to CSN Low Setup Time: CSN Low to SCLK High Rising Time: CSN,SCLK Falling Time: CSN,SCLK Symbol 1/tPSCLK tWSH tWSL tWCL tHCS tSCS tR tF 40 40 16 80 40 100 100 Min Typ Max 4
[AK2306/LV]
Units Ref fig MHz ns ns SCL K ns ns ns ns Fig4
WRITE
Setup Time: DATA to SCLK High Hold Time: SCLK High to DATA Hold Time: SCLK Low to CSN High tSDC tHDC tHCS2 40 40 0 ns ns ns Fig4
READ
Delay Time: SCLK Low to DATA pin drive Delay Time: SCLK Low to DATA valid Delay Time: SCLK Low to DATA High-Z Delay Time: CSN High to DATA High-Z CSN Pulse Width High tDDD tDVD tDZSD tDZCD tWCH 0 0 40 0 60 60 60 ns Fig5 ns ns ns ns Fig6
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ASAHI KASEI
tWCL
[AK2306/LV]
CSN
tHCS tWSH tWSL tPSCLK tF tR tHCS
SCLK
tHDC tSC tSD
DATA
I3
I2
I0
A2
A0
*
D7
D6 - D1
D0
Fig4 Serial Interface Timing
tWCL

CSN
tHCS tWSH tWSL tPSCLK tF tR tHCS2
SCLK
tHDC tSC tSD tDDD Z I2 I0 A2 A0 D7 D6 D1 D0 tDVD
DATA
I3
Fig5 Serial Interface Timing
tWCH

CSN
SCLK
tDZSD tDZCD Z Z
DATA
D1
D0
I1
I0
D0
Fig6 Serial Interface Timing
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ASAHI KASEI
[AK2306/LV]
APPLICATION CIRCUIT EXAMPLE
Analog input circuit(AMPT0,1) AK2306/LV has an op-amp at analog input of each channel. Each op-amp can be used as a gain adjustment. Op-amp can be used as an inverting amplifier or differential input buffer with AMPRn as VREF buffer . Feedback resistor must be 10k ohm or larger. Single End buffer AK2306 GSXn R2 (n=0,1) C1 R1 VFXn
C1=0.47uF R1=R2=33kohm
AMPTn BGREF
more than 1.0uF
Differential buffer
GSXn R2 C1 R1 VFXn (n=0,1)
AMPTn R1 R2 C1=0.47uF R1=R2=33kohm
AMPRn ! Important Notice
BGREF
Please use AMPRn as a AGND buffer to avoid a cross talk between TX and RX, channel1 and channel2 when TX input is composed as a differential input.
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ASAHI KASEI
[AK2306/LV]
Analog output circuit(AMPR0,1) AK2306/LV has an op-amp at analog output stage of each channel to consist in an inverting amplifier for a gain adjustment of 0dBm0 level. Feedback resistor must be 10kohm or larger. AK2306 GSRn BGREF (n=0,1) R1 R1=R2=33kohm R2 VRn GAnR VFRn
! Important Notice
When AMPRn are used as a AGND buffer, they can not be used for a gain adjustment.
Analog ground stabilization capacitor An external capacitor of more than 1.0uF should be connected between VREF and VSS to stabilize analog ground (VREF).
AK2306/LV VREF C +
PLL Loop filter capcitor An external capacitor of more than 0.22uF should be connected between LPC and VSS.
AK2306/LV LPC C +
Power Supply To attenuate the power supply noise, connect capacitors between VDD and VSS, as shown below. AK2306/LV VDD C1 VSS + C2 C1=C3=0.1uF C2=C4=10uF
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ASAHI KASEI
[AK2306/LV]
PACKAGE INFORMATION
- 24pin VSOP Marking (1) Date Code: 5 digit XXXXX (2) Marketing Code: AK2306/AK2306LV (3) AKM Logo
AKM AK2306 XXXXX
AKM AK2306LV XXXXX
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ASAHI KASEI
PACKAGE SIZE
[AK2306/LV]
24pin VSOP (Unit: mm)
*7.90.2
24
13 A 7.60.2 0.15+0.10 -0.05 0.100.05 Detail A 0.50.2 0-10
37 2001/11
1
12 0.65
0.12
0.22+0.10 -0.05 M
1.150.10 Seating Plane 0.08
NOTE: Dimension "*" does not include mold flash.
MS0093-E-04
5.6
ASAHI KASEI
[AK2306/LV]
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
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